The present invention relates, in general, to the field of integrated circuit memories. More particularly, the present invention relates to a method and apparatus for operating an integrated circuit memory array in a first, single memory cell per bit operational mode and in a second, two or multi-memory cell per bit operational mode.
A typical “1T/1C” memory cell 10 that forms part of an array of such cells for a typical DRAM integrated circuit memory is shown in FIG. 1. Memory cell 10 includes an access transistor M1 for reading data from or writing data to storage capacitor C1. A source/drain of transistor M1 is coupled to the bit line BL, and the gate of transistor M1 is coupled to the word line WL. Only one memory cell, word line, and bit line is shown, although it is apparent to those skilled in the art that there are a plurality of word lines, bit lines, and memory cells arranged in rows and columns in a typical DRAM memory array. An array of 1T/1C memory cells of the type shown in FIG. 1 is preferred since these cells provide a single data bit for the smallest amount of integrated circuit die area.
A “2T/2C” memory cell 20 that forms part of an array of such cells for a DRAM integrated circuit memory is shown in FIG. 2. Memory cell 20 includes two access transistor M1 and M2 for reading data from or writing data to storage capacitors C1 and C2. A source/drain of transistor M1 is coupled to the bit line BL, and the gate of transistor M1 is coupled to a first word line WL1. A source/drain of transistor M2 is coupled to the complementary bit line/BL, and the gate of transistor M2 is coupled to the word line WL2. Only two memory cells, two word lines, and two bit lines are shown, although it is apparent to those skilled in the art that there are a plurality of word lines, bit lines, and memory cells arranged in rows and columns in a 2T/2C DRAM memory array. An array of 2T/2C memory cells of the type shown in FIG. 2 is not preferred in most cases since these cells provide a single data bit for double the amount of integrated circuit die area compared to a 1T/1C array. There are some cases, however, in which the lower density but greater signal strength and other concomitant advantages of a 2T/2C memory are desired.
Prior art techniques have been developed for operating an array of memory cells as both an array of 1T/1C memory cells in a first operational mode and an array of 2T/2C memory cells in a second operational mode. One prior art technique teaches a method of adding extra pass gates to the edges of the DRAM subarray that changes which bit lines are compared by the sense amplifiers for a normal operating mode and for the twin-cell operating mode. While such a technique can provide both operational modes, it can be difficult to go between the regular mode and the twin cell mode. Also, extra switching devices not normally used in the memory array are required at the array edge. These extra devices are not symmetrical on the BL and/BL bit lines and cause capacitance imbalances. Also, the gates of these devices need to be switched in an AC manner and reduce chip speed and increase chip power. Prior art techniques such as the one described above cannot be extended to four or more cells per bit and are limited to either one or two cells per bit.
What is desired is a method of operating an integrated circuit memory array that easily switches between a single memory cell per bit operating mode to a two or more memory cell per bit operating mode, without the capacitor imbalance, complicated circuitry, or other restrictions found in prior art techniques.